Embedded Processor

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Thursday, December 10, 2009

Atrenta - Early Design Closure ASIC Design

Atrenta - Early Design Closure ASIC Design

".. tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. "

SpyGlass - Early Design Analysis for Logic Designers - Atrenta

"Using advanced static and dynamic analysis, the SpyGlass solution pinpoints structural, coding and consistency problems at RTL. In addition, the solution offers the industy's most comprehensive solution for analysis of clock, reset and clock domain crossings (CDC)."

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